Intel announces 45nm breakthrough
1/27/2007 2:17:45 PM, by Jon Stokes
It's a shame that Intel happened to pick a Saturday when I'm trying to move to make major news with their upcoming 45nm process. This means that I can't do more than quickly summarize what was announced, but I can point you to two good articles that can take you further if you want to know more.
In a nutshell, Intel has announced a pair of advances in their 45nm process that will cut down drastically on leakage current (see below for more), enabling the company to make the transistors on their next generation of chips much smaller without worrying so much about current bleeding through when the transistor is in the "off" position. The first of these advances is the use of a high-k gate dielectric, a first in commercial semiconductor production. The dielectric is essentially an insulator that can now be made very thin without allowing electrical current to seep through (due to quantum tunneling) when the transistor is in the "off" position.
To complement this high-k dielectric, Intel has also moved to a metal gate electrode. This metal gate electrode is more compatible with the new hafnium-based dielectric than the polysilicon electrode used in previous process steps.
The new 45nm process will be used for Intel's forthcoming Penryn microarchitecture, which is basically just a die shrink of Woodcrest with more cache.
According to David Kanter at RealWorldTech, IBM and AMD don't plan to move to a similar high-k dielectric until the 32nm process node, a decision that may put them at a disadvantage versus Intel at 45 nanometers. Kanter summarizes the situation as follows:
The high-k dielectrics and metal gates will give Intel an advantage on their 45nm process. However, this transistor level advantage will not directly translate to microprocessor performance, without corresponding advances or clever engineering to address wire delay. It will be up to Intel's MPU designers and marketers to make the most of these benefits, by increasing clock speed or reducing power. The real question is whether the combination of high-k dielectrics and metal gates will shut the window of opportunity for AMD, when they introduce their own 45nm process in mid to late 2008, and only time will tell where the chips will fall.
For an in-depth look at the new announcements, be sure and head over to RWT and read David's article. If you want a more high-level overview with more background and big-picture perspective than I've provided here, John Markoff at the New York Times has a good piece on it that's worth checking out. Also, Robert Scoble has a video tour of the new fab if you're interested in seeing where all the magic happens.
Leakage current and clockspeed: a primer
When you're reading up on this announcement, many of you will probably need a refresher on the relationship between feature size, leakage current, power dissipation, and clockspeed. To help you out, I'm going to paste in a short discussion of power density from one version of Chapter 12 of my book, Inside the Machine. (I'm not sure if this is the final copy that's in the book or not, though, since I'd have to hunt around and compare this text with what's in the proofs).
The amount of power that a chip dissipates per unit area is called its power density, and there are two types of power density that concern processor architects: dynamic power density and static power density.
Dynamic Power Density
Each transistor on a chip dissipates a small amount of power when it is switched, and transistors that are switched rapidly dissipate more power than transistors that are switched slowly. The total amount of power dissipated per unit area due to switching of a chip's transistors is called dynamic power density. There are two factors that work together to cause an increase in dynamic power density: clockspeed and transistor density.
Increasing a processor's clockspeed involves switching its transistors more rapidly, and as I just mentioned, transistors that are switched more rapidly dissipate more power. Therefore, as a processor's clockspeed rises, so does its dynamic power density, because each of those rapidly switching transistors contributes more to the device's total power dissipation. You can also increase a chip's dynamic power density by cramming more transistors into the same amount of surface area.
Figure 12-1 illustrates how transistor density and clockspeed work together to increase dynamic power density. As the clockspeed of the device and the number of transistors per unit area rise, so does the overall dynamic power density.
Figure 12-1: Dynamic power density Static Power Density
In addition to clockspeed-related increases in dynamic power density, chip designers must also contend with the fact that even transistors that aren't switching will still leak current during idle periods, much like how a faucet that is shut off can still leak water if the water pressure behind it is high enough. This leakage current causes an idle transistor to constantly dissipate a trace amount of power. The amount of power dissipated per unit area due to leakage current is called static power density.
Transistors leak more current as they get smaller, and consequently static power densities begin to rise across the chip when more transistors are crammed into the same amount of space. Thus even relatively low clockspeed devices with very small transistor sizes are still subject to increases in power density if leakage current is not controlled. If a silicon device's overall power density gets high enough, it will begin to overheat and will eventually fail entirely. Thus it's critical that designers of highly integrated devices like modern x86 processors take power efficiency into account when designing a new microarchitecture.